3 Commits

Include renames

Author	SHA1	Message	Date
soconnor	b0c57a8a7e	Fix ALU: Use out pin directly instead of internal finalout bus ... - Removed invalid finalout internal bus - Use out[0..7], out[8..15], out[15] directly for flag computation - Fixes HDL sub-bus restriction error	2025-09-01 15:03:26 -04:00
soconnor	2b3da7a171	Implement Project 2: Arithmetic Logic Unit ... ✅ HalfAdder: XOR for sum, AND for carry ✅ FullAdder: Two half adders + OR ✅ Add16: Chain of 16 full adders with carry ✅ Inc16: Add16 with constant 1 ✅ ALU: Complete arithmetic logic unit with all operations Used concise, student-style comments throughout.	2025-08-30 19:49:23 -04:00
soconnor	4563dd234b	Add project 2 template files	2025-08-30 19:47:34 -04:00