Fix ALU: Use out pin directly instead of internal finalout bus

- Removed invalid finalout internal bus
- Use out[0..7], out[8..15], out[15] directly for flag computation
- Fixes HDL sub-bus restriction error

02/ALU.hdl

@@ -41,35 +41,35 @@ CHIP ALU {
         ng;      // if (out < 0)  equals 1, else 0
 
     PARTS:
-    // Step 1: Handle zx (zero x)
+    // handle zx (zero x)
     Mux16(a=x, b=false, sel=zx, out=x1);
 
-    // Step 2: Handle nx (negate x)
+    // handle nx (negate x)
     Not16(in=x1, out=notx1);
     Mux16(a=x1, b=notx1, sel=nx, out=x2);
 
-    // Step 3: Handle zy (zero y)
+    // handle zy (zero y)
     Mux16(a=y, b=false, sel=zy, out=y1);
 
-    // Step 4: Handle ny (negate y)
+    // handle ny (negate y)
     Not16(in=y1, out=noty1);
     Mux16(a=y1, b=noty1, sel=ny, out=y2);
 
-    // Step 5: Handle f (function: add or and)
+    // handle f (add or and)
     Add16(a=x2, b=y2, out=addout);
     And16(a=x2, b=y2, out=andout);
     Mux16(a=andout, b=addout, sel=f, out=fout);
 
-    // Step 6: Handle no (negate output)
+    // handle no (negate out)
     Not16(in=fout, out=notfout);
-    Mux16(a=fout, b=notfout, sel=no, out=out, out=finalout);
+    Mux16(a=fout, b=notfout, sel=no, out=out);
 
-    // Step 7: Compute zr (zero flag)
-    Or8Way(in=finalout[0..7], out=tmp1);
-    Or8Way(in=finalout[8..15], out=tmp2);
+    // compute zr (zero flag)
+    Or8Way(in=out[0..7], out=tmp1);
+    Or8Way(in=out[8..15], out=tmp2);
     Or(a=tmp1, b=tmp2, out=notzr);
     Not(in=notzr, out=zr);
 
-    // Step 8: Compute ng (negative flag)
-    And(a=finalout[15], b=true, out=ng);
+    // compute ng (negative flag)
+    And(a=out[15], b=true, out=ng);
 }

02/Add16.hdl

@@ -11,7 +11,6 @@ CHIP Add16 {
     OUT out[16];
 
     PARTS:
-    // Chain 16 FullAdders with carry propagation
     HalfAdder(a=a[0], b=b[0], sum=out[0], carry=c0);
     FullAdder(a=a[1], b=b[1], c=c0, sum=out[1], carry=c1);
     FullAdder(a=a[2], b=b[2], c=c1, sum=out[2], carry=c2);

02/Add16.out

@@ -0,0 +1,7 @@
+|        a         |        b         |       out        |
+| 0000000000000000 | 0000000000000000 | 0000000000000000 |
+| 0000000000000000 | 1111111111111111 | 1111111111111111 |
+| 1111111111111111 | 1111111111111111 | 1111111111111110 |
+| 1010101010101010 | 0101010101010101 | 1111111111111111 |
+| 0011110011000011 | 0000111111110000 | 0100110010110011 |
+| 0001001000110100 | 1001100001110110 | 1010101010101010 |

02/FullAdder.hdl

@@ -11,7 +11,6 @@ CHIP FullAdder {
         carry;   // Left bit of a + b + c
 
     PARTS:
-    // Two half adders + OR gate
     HalfAdder(a=a, b=b, sum=tmp1, carry=tmp2);
     HalfAdder(a=tmp1, b=c, sum=sum, carry=tmp3);
     Or(a=tmp2, b=tmp3, out=carry);

02/HalfAdder.out

@@ -0,0 +1,5 @@
+| a | b |sum|car|
+| 0 | 0 | 0 | 0 |
+| 0 | 1 | 1 | 0 |
+| 1 | 0 | 1 | 0 |
+| 1 | 1 | 0 | 1 |

02/Inc16.hdl

@@ -11,6 +11,6 @@ CHIP Inc16 {
     OUT out[16];
 
     PARTS:
-    // Add 1 using Add16
+    // out = in + 1
     Add16(a=in, b[0]=true, b[1..15]=false, out=out);
 }