e784e8380f
update .gitignore
2025-10-26 18:05:19 -04:00
38f08d2b54
project08 - copy project07 hvm.py
2025-10-26 18:04:02 -04:00
38721f77c0
project08 template files
2025-10-26 17:51:57 -04:00
be00f40a6b
project07 complete
2025-10-26 17:51:41 -04:00
3092f1e11b
Add VM to Hack assembly translator
2025-10-24 15:38:34 -04:00
c2eb5f198a
project07 - add project files
2025-10-07 22:11:24 -04:00
ed1df6332a
Add Hack assembler implementation and project files
2025-10-06 23:49:11 -04:00
1853f8070e
project06 - add files
2025-09-22 23:20:42 -04:00
114ba7ade3
project 5.5 - complete
2025-09-22 23:20:34 -04:00
3c0620d3d4
project 5.5 - file addition
2025-09-22 23:12:57 -04:00
516d1878cb
project05 - complete
2025-09-22 15:17:34 -04:00
2d65af2101
Update .gitignore
2025-09-18 22:56:57 -04:00
1bc427b545
project05: base files
2025-09-10 15:49:03 -04:00
e21e7d0d55
project04: fillstatic
2025-09-10 15:48:57 -04:00
4025e16dd8
project04: complete
2025-09-10 15:48:45 -04:00
2231d4c97c
project04: Complete fill.asm
2025-09-08 15:05:25 -04:00
b447557af8
project04: Complete mult.asm
2025-09-06 18:55:52 -04:00
1e536422b8
project03: Comments/cleanup
2025-09-03 23:02:45 -04:00
e1c0b091a8
project02: Comments/cleanup
2025-09-03 22:55:08 -04:00
934f1ad2f5
project01: Comments/cleanup
2025-09-03 22:10:34 -04:00
dd31b8f1dc
project04: add template files
2025-09-03 10:45:45 -04:00
d0c67845f4
project03: Compound RAM chips
2025-09-03 10:45:00 -04:00
e485868265
project03 - create bit, register, and program counter
2025-09-03 10:19:05 -04:00
22e0b42305
Update ALU comments
2025-09-03 10:18:19 -04:00
c2cea97f87
add project03 base files
2025-09-02 08:33:16 -04:00
2e8ebbbfd5
project02 complete, add .gitignore
2025-09-02 08:33:07 -04:00
e389939297
Fix ALU: Properly split output for flag computation
...
- Use out=out, out[0..7]=outLow, out[8..15]=outHigh, out[15]=sign syntax
- Compute flags using internal signals outLow, outHigh, sign
- Avoids HDL restriction on using output pins as inputs
2025-09-01 15:05:16 -04:00
b0c57a8a7e
Fix ALU: Use out pin directly instead of internal finalout bus
...
- Removed invalid finalout internal bus
- Use out[0..7], out[8..15], out[15] directly for flag computation
- Fixes HDL sub-bus restriction error
2025-09-01 15:03:26 -04:00
2b3da7a171
Implement Project 2: Arithmetic Logic Unit
...
✅ HalfAdder: XOR for sum, AND for carry
✅ FullAdder: Two half adders + OR
✅ Add16: Chain of 16 full adders with carry
✅ Inc16: Add16 with constant 1
✅ ALU: Complete arithmetic logic unit with all operations
Used concise, student-style comments throughout.
2025-08-30 19:49:23 -04:00
4563dd234b
Add project 2 template files
2025-08-30 19:47:34 -04:00
f43ce1f964
Remove redundant comments from logic gate HDL files
2025-08-30 19:45:03 -04:00
396902dee7
Replace De Morgan's law comment with basic Or logic description
2025-08-30 19:23:29 -04:00
c39ce212b4
Simplify comments to be more concise and student-like
...
- Removed verbose explanations
- Made comments shorter and more casual
- Focus on key concepts rather than formal descriptions
2025-08-28 15:11:48 +02:00
ecdc6ab2bc
Refactor: Use simple tmp variable names instead of descriptive ones
...
- Changed nandOut -> tmp
- Changed notA, notB -> tmp1, tmp2
- Changed descriptive names -> tmp1, tmp2, tmp3, etc.
Makes code cleaner and more concise while maintaining functionality.
2025-08-28 14:39:07 +02:00
085a90e4c8
Project 1 Complete: All 15 logic gates implemented
...
✅ Basic Gates (6):
- Not, And, Or, Xor, Mux, DMux
✅ 16-bit Gates (4):
- Not16, And16, Or16, Mux16
✅ Multi-way Gates (5):
- Or8Way, Mux4Way16, Mux8Way16, DMux4Way, DMux8Way
All gates built using only NAND gates and previously implemented gates.
2025-08-28 13:19:52 +02:00
88b4cc4ad9
Implement multi-way gates: Or8Way, Mux4Way16, Mux8Way16, DMux4Way, DMux8Way
2025-08-28 13:19:40 +02:00
93f730d0ce
Implement 16-bit logic gates: Not16, And16, Or16, Mux16
2025-08-27 19:08:17 +02:00
ad5f774ae0
Implement basic logic gates: Not, And, Or, Xor, Mux, DMux
2025-08-27 19:07:20 +02:00
beb668806a
Initial commit: Project 0 completed, Project 1 skeleton files
2025-08-27 19:05:53 +02:00
