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https://github.com/soconnor0919/nand2tetris-zed.git
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Clean up extension and update repository references
- Removed duplicate WASM files and build artifacts - Cleaned up test files and temporary files - Updated all grammar repositories with READMEs and .gitignore - All repositories now have proper documentation and are clean
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Submodule grammars/compare_output updated: 51fd3069d1...7d2f99db03
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Submodule grammars/hack_assembly updated: 74f44fa77e...a2442f53ea
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Submodule grammars/hack_binary updated: d408c50827...c4034857c7
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Submodule grammars/hdl updated: 2199fdf1d3...36da989403
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Submodule grammars/jack updated: 1a617413ea...c2d0dbbe79
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Submodule grammars/test_script updated: 909bf1dfe8...0a17b7ae9a
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Submodule grammars/vm updated: 615f50fc59...85399605df
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grammars/vm.wasm
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grammars/vm.wasm
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Submodule grammars/xml updated: 1e86bc6d16...4c8286def0
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@@ -1,6 +0,0 @@
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@2
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D=A
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@3
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D=D+A
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@0
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M=D
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29
test-hdl.hdl
29
test-hdl.hdl
@@ -1,29 +0,0 @@
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// Test HDL file for syntax highlighting
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/**
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* Example chip demonstrating various HDL syntax patterns
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*/
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CHIP TestChip {
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IN in[16], // 16-bit input
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load, // control signal
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address[3]; // 3-bit address
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OUT out[16], // 16-bit output
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ready; // status signal
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PARTS:
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// Built-in chip reference
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BUILTIN ALU;
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// Clocked body
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CLOCKED DFF, Register;
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// Part instantiation with connections
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Mux16(a=in, b=out, sel=load, out=muxOut);
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// Register with bus connections
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Register(in=muxOut, load=load, out=out);
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// Complex connection
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ALU(x=in, y=out, zx=load, nx=false, zy=true, ny=false,
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f=true, no=false, out=aluOut, zr=zero, ng=negative);
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}
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