e1c0b091a8
project02: Comments/cleanup
2025-09-03 22:55:08 -04:00
22e0b42305
Update ALU comments
2025-09-03 10:18:19 -04:00
2e8ebbbfd5
project02 complete, add .gitignore
2025-09-02 08:33:07 -04:00
e389939297
Fix ALU: Properly split output for flag computation
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- Use out=out, out[0..7]=outLow, out[8..15]=outHigh, out[15]=sign syntax
- Compute flags using internal signals outLow, outHigh, sign
- Avoids HDL restriction on using output pins as inputs
2025-09-01 15:05:16 -04:00
b0c57a8a7e
Fix ALU: Use out pin directly instead of internal finalout bus
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- Removed invalid finalout internal bus
- Use out[0..7], out[8..15], out[15] directly for flag computation
- Fixes HDL sub-bus restriction error
2025-09-01 15:03:26 -04:00
2b3da7a171
Implement Project 2: Arithmetic Logic Unit
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✅ HalfAdder: XOR for sum, AND for carry
✅ FullAdder: Two half adders + OR
✅ Add16: Chain of 16 full adders with carry
✅ Inc16: Add16 with constant 1
✅ ALU: Complete arithmetic logic unit with all operations
Used concise, student-style comments throughout.
2025-08-30 19:49:23 -04:00
4563dd234b
Add project 2 template files
2025-08-30 19:47:34 -04:00
