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Remove redundant comments from logic gate HDL files
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@@ -11,7 +11,6 @@ CHIP Xor {
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OUT out;
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PARTS:
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// Xor = (a AND !b) OR (!a AND b)
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Not(in=a, out=tmp1);
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Not(in=b, out=tmp2);
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And(a=a, b=tmp2, out=tmp3);
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