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Remove redundant comments from logic gate HDL files
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@@ -20,7 +20,6 @@ CHIP Mux8Way16 {
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OUT out[16];
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PARTS:
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// Two Mux4Way16 + one Mux16
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Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=tmp1);
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Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=tmp2);
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Mux16(a=tmp1, b=tmp2, sel=sel[2], out=out);
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