Remove redundant comments from logic gate HDL files

01/And16.hdl

@@ -12,7 +12,6 @@ CHIP And16 {
     OUT out[16];
 
     PARTS:
-    // And each bit
     And(a=a[0], b=b[0], out=out[0]);
     And(a=a[1], b=b[1], out=out[1]);
     And(a=a[2], b=b[2], out=out[2]);