Remove redundant comments from logic gate HDL files

01/And16.hdl

@@ -12,7 +12,6 @@ CHIP And16 {
     OUT out[16];
 
     PARTS:
-    // And each bit
     And(a=a[0], b=b[0], out=out[0]);
     And(a=a[1], b=b[1], out=out[1]);
     And(a=a[2], b=b[2], out=out[2]);

01/DMux.hdl

@@ -12,7 +12,6 @@ CHIP DMux {
     OUT a, b;
 
     PARTS:
-    // sel=0 sends to a, sel=1 sends to b
     Not(in=sel, out=tmp);
     And(a=in, b=tmp, out=a);
     And(a=in, b=sel, out=b);

01/DMux4Way.hdl

@@ -14,7 +14,6 @@ CHIP DMux4Way {
     OUT a, b, c, d;
 
     PARTS:
-    // Two levels of DMux
     DMux(in=in, sel=sel[1], a=tmp1, b=tmp2);
     DMux(in=tmp1, sel=sel[0], a=a, b=b);
     DMux(in=tmp2, sel=sel[0], a=c, b=d);

01/DMux4Way.out

@@ -0,0 +1,9 @@
+|in | sel  | a | b | c | d |
+| 0 |  00  | 0 | 0 | 0 | 0 |
+| 0 |  01  | 0 | 0 | 0 | 0 |
+| 0 |  10  | 0 | 0 | 0 | 0 |
+| 0 |  11  | 0 | 0 | 0 | 0 |
+| 1 |  00  | 1 | 0 | 0 | 0 |
+| 1 |  01  | 0 | 1 | 0 | 0 |
+| 1 |  10  | 0 | 0 | 1 | 0 |
+| 1 |  11  | 0 | 0 | 0 | 1 |

01/DMux8Way.hdl

@@ -18,7 +18,6 @@ CHIP DMux8Way {
     OUT a, b, c, d, e, f, g, h;
 
     PARTS:
-    // One DMux + two DMux4Way
     DMux(in=in, sel=sel[2], a=tmp1, b=tmp2);
     DMux4Way(in=tmp1, sel=sel[0..1], a=a, b=b, c=c, d=d);
     DMux4Way(in=tmp2, sel=sel[0..1], a=e, b=f, c=g, d=h);

01/Mux.hdl

@@ -11,7 +11,6 @@ CHIP Mux {
     OUT out;
 
     PARTS:
-    // sel=0 picks a, sel=1 picks b
     Not(in=sel, out=tmp1);
     And(a=a, b=tmp1, out=tmp2);
     And(a=b, b=sel, out=tmp3);

01/Mux16.hdl

@@ -12,7 +12,6 @@ CHIP Mux16 {
     OUT out[16];
 
     PARTS:
-    // Mux each bit
     Mux(a=a[0], b=b[0], sel=sel, out=out[0]);
     Mux(a=a[1], b=b[1], sel=sel, out=out[1]);
     Mux(a=a[2], b=b[2], sel=sel, out=out[2]);

01/Mux4Way16.hdl

@@ -14,7 +14,6 @@ CHIP Mux4Way16 {
     OUT out[16];
 
     PARTS:
-    // Two levels of Mux16
     Mux16(a=a, b=b, sel=sel[0], out=tmp1);
     Mux16(a=c, b=d, sel=sel[0], out=tmp2);
     Mux16(a=tmp1, b=tmp2, sel=sel[1], out=out);

01/Mux8Way16.hdl

@@ -20,7 +20,6 @@ CHIP Mux8Way16 {
     OUT out[16];
 
     PARTS:
-    // Two Mux4Way16 + one Mux16
     Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=tmp1);
     Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=tmp2);
     Mux16(a=tmp1, b=tmp2, sel=sel[2], out=out);

01/Not.hdl

@@ -11,6 +11,6 @@ CHIP Not {
     OUT out;
 
     PARTS:
-    // Not = Nand with same input
+    // Not = Nand same input
     Nand(a=in, b=in, out=out);
 }

01/Not16.hdl

@@ -12,7 +12,6 @@ CHIP Not16 {
     OUT out[16];
 
     PARTS:
-    // Not each bit
     Not(in=in[0], out=out[0]);
     Not(in=in[1], out=out[1]);
     Not(in=in[2], out=out[2]);

01/Or16.hdl

@@ -12,7 +12,6 @@ CHIP Or16 {
     OUT out[16];
 
     PARTS:
-    // Or each bit
     Or(a=a[0], b=b[0], out=out[0]);
     Or(a=a[1], b=b[1], out=out[1]);
     Or(a=a[2], b=b[2], out=out[2]);

01/Or8Way.hdl

@@ -11,7 +11,6 @@ CHIP Or8Way {
     OUT out;
 
     PARTS:
-    // Chain Or gates
     Or(a=in[0], b=in[1], out=tmp1);
     Or(a=in[2], b=in[3], out=tmp2);
     Or(a=in[4], b=in[5], out=tmp3);

01/Xor.hdl

@@ -11,7 +11,6 @@ CHIP Xor {
     OUT out;
 
     PARTS:
-    // Xor = (a AND !b) OR (!a AND b)
     Not(in=a, out=tmp1);
     Not(in=b, out=tmp2);
     And(a=a, b=tmp2, out=tmp3);