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https://github.com/soconnor0919/eceg431.git
synced 2025-12-11 06:34:43 -05:00
Refactor: Use simple tmp variable names instead of descriptive ones
- Changed nandOut -> tmp - Changed notA, notB -> tmp1, tmp2 - Changed descriptive names -> tmp1, tmp2, tmp3, etc. Makes code cleaner and more concise while maintaining functionality.
This commit is contained in:
@@ -12,6 +12,6 @@ CHIP And {
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PARTS:
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// And(a,b) = Not(Nand(a,b))
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Nand(a=a, b=b, out=nandOut);
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Not(in=nandOut, out=out);
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Nand(a=a, b=b, out=tmp);
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Not(in=tmp, out=out);
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}
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@@ -13,7 +13,7 @@ CHIP DMux {
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PARTS:
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// DMux(in,sel) -> a = And(in, Not(sel)), b = And(in, sel)
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Not(in=sel, out=notSel);
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And(a=in, b=notSel, out=a);
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Not(in=sel, out=tmp);
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And(a=in, b=tmp, out=a);
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And(a=in, b=sel, out=b);
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}
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@@ -15,7 +15,7 @@ CHIP DMux4Way {
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PARTS:
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// Use two levels of DMux: first level splits by sel[1], second level splits by sel[0]
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DMux(in=in, sel=sel[1], a=dmuxAB, b=dmuxCD);
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DMux(in=dmuxAB, sel=sel[0], a=a, b=b);
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DMux(in=dmuxCD, sel=sel[0], a=c, b=d);
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DMux(in=in, sel=sel[1], a=tmp1, b=tmp2);
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DMux(in=tmp1, sel=sel[0], a=a, b=b);
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DMux(in=tmp2, sel=sel[0], a=c, b=d);
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}
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@@ -19,7 +19,7 @@ CHIP DMux8Way {
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PARTS:
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// Use one DMux and two DMux4Way gates: first split by sel[2], then each half by sel[0..1]
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DMux(in=in, sel=sel[2], a=dmuxABCD, b=dmuxEFGH);
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DMux4Way(in=dmuxABCD, sel=sel[0..1], a=a, b=b, c=c, d=d);
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DMux4Way(in=dmuxEFGH, sel=sel[0..1], a=e, b=f, c=g, d=h);
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DMux(in=in, sel=sel[2], a=tmp1, b=tmp2);
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DMux4Way(in=tmp1, sel=sel[0..1], a=a, b=b, c=c, d=d);
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DMux4Way(in=tmp2, sel=sel[0..1], a=e, b=f, c=g, d=h);
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}
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@@ -12,8 +12,8 @@ CHIP Mux {
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PARTS:
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// Mux(a,b,sel) = Or(And(a, Not(sel)), And(b, sel))
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Not(in=sel, out=notSel);
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And(a=a, b=notSel, out=aAndNotSel);
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And(a=b, b=sel, out=bAndSel);
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Or(a=aAndNotSel, b=bAndSel, out=out);
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Not(in=sel, out=tmp1);
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And(a=a, b=tmp1, out=tmp2);
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And(a=b, b=sel, out=tmp3);
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Or(a=tmp2, b=tmp3, out=out);
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}
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@@ -15,7 +15,7 @@ CHIP Mux4Way16 {
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PARTS:
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// Use two levels of Mux16: first level selects between pairs, second level selects final output
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Mux16(a=a, b=b, sel=sel[0], out=muxAB);
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Mux16(a=c, b=d, sel=sel[0], out=muxCD);
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Mux16(a=muxAB, b=muxCD, sel=sel[1], out=out);
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Mux16(a=a, b=b, sel=sel[0], out=tmp1);
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Mux16(a=c, b=d, sel=sel[0], out=tmp2);
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Mux16(a=tmp1, b=tmp2, sel=sel[1], out=out);
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}
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@@ -21,7 +21,7 @@ CHIP Mux8Way16 {
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PARTS:
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// Use two Mux4Way16 gates and one Mux16 to select from 8 inputs
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Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=mux4wayABCD);
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Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=mux4wayEFGH);
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Mux16(a=mux4wayABCD, b=mux4wayEFGH, sel=sel[2], out=out);
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Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=tmp1);
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Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=tmp2);
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Mux16(a=tmp1, b=tmp2, sel=sel[2], out=out);
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}
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@@ -12,8 +12,8 @@ CHIP Or {
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PARTS:
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// Or(a,b) = Not(And(Not(a), Not(b))) - De Morgan's law
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Not(in=a, out=notA);
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Not(in=b, out=notB);
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And(a=notA, b=notB, out=andOut);
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Not(in=andOut, out=out);
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Not(in=a, out=tmp1);
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Not(in=b, out=tmp2);
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And(a=tmp1, b=tmp2, out=tmp3);
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Not(in=tmp3, out=out);
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}
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@@ -12,11 +12,11 @@ CHIP Or8Way {
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PARTS:
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// Chain Or gates to combine all 8 inputs
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Or(a=in[0], b=in[1], out=or01);
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Or(a=in[2], b=in[3], out=or23);
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Or(a=in[4], b=in[5], out=or45);
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Or(a=in[6], b=in[7], out=or67);
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Or(a=or01, b=or23, out=or0123);
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Or(a=or45, b=or67, out=or4567);
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Or(a=or0123, b=or4567, out=out);
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Or(a=in[0], b=in[1], out=tmp1);
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Or(a=in[2], b=in[3], out=tmp2);
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Or(a=in[4], b=in[5], out=tmp3);
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Or(a=in[6], b=in[7], out=tmp4);
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Or(a=tmp1, b=tmp2, out=tmp5);
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Or(a=tmp3, b=tmp4, out=tmp6);
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Or(a=tmp5, b=tmp6, out=out);
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}
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10
01/Xor.hdl
10
01/Xor.hdl
@@ -12,9 +12,9 @@ CHIP Xor {
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PARTS:
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// Xor(a,b) = Or(And(a, Not(b)), And(Not(a), b))
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Not(in=a, out=notA);
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Not(in=b, out=notB);
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And(a=a, b=notB, out=aAndNotB);
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And(a=notA, b=b, out=notAAndB);
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Or(a=aAndNotB, b=notAAndB, out=out);
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Not(in=a, out=tmp1);
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Not(in=b, out=tmp2);
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And(a=a, b=tmp2, out=tmp3);
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And(a=tmp1, b=b, out=tmp4);
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Or(a=tmp3, b=tmp4, out=out);
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}
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