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https://github.com/soconnor0919/eceg431.git
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Fix ALU: Use out pin directly instead of internal finalout bus
- Removed invalid finalout internal bus - Use out[0..7], out[8..15], out[15] directly for flag computation - Fixes HDL sub-bus restriction error
This commit is contained in:
24
02/ALU.hdl
24
02/ALU.hdl
@@ -41,35 +41,35 @@ CHIP ALU {
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ng; // if (out < 0) equals 1, else 0
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PARTS:
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// Step 1: Handle zx (zero x)
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// handle zx (zero x)
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Mux16(a=x, b=false, sel=zx, out=x1);
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// Step 2: Handle nx (negate x)
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// handle nx (negate x)
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Not16(in=x1, out=notx1);
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Mux16(a=x1, b=notx1, sel=nx, out=x2);
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// Step 3: Handle zy (zero y)
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// handle zy (zero y)
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Mux16(a=y, b=false, sel=zy, out=y1);
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// Step 4: Handle ny (negate y)
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// handle ny (negate y)
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Not16(in=y1, out=noty1);
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Mux16(a=y1, b=noty1, sel=ny, out=y2);
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// Step 5: Handle f (function: add or and)
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// handle f (add or and)
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Add16(a=x2, b=y2, out=addout);
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And16(a=x2, b=y2, out=andout);
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Mux16(a=andout, b=addout, sel=f, out=fout);
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// Step 6: Handle no (negate output)
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// handle no (negate out)
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Not16(in=fout, out=notfout);
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Mux16(a=fout, b=notfout, sel=no, out=out, out=finalout);
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Mux16(a=fout, b=notfout, sel=no, out=out);
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// Step 7: Compute zr (zero flag)
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Or8Way(in=finalout[0..7], out=tmp1);
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Or8Way(in=finalout[8..15], out=tmp2);
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// compute zr (zero flag)
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Or8Way(in=out[0..7], out=tmp1);
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Or8Way(in=out[8..15], out=tmp2);
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Or(a=tmp1, b=tmp2, out=notzr);
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Not(in=notzr, out=zr);
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// Step 8: Compute ng (negative flag)
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And(a=finalout[15], b=true, out=ng);
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// compute ng (negative flag)
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And(a=out[15], b=true, out=ng);
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}
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