// Test HDL file for syntax highlighting
/**
 * Example chip demonstrating various HDL syntax patterns
 */
CHIP TestChip {
    IN  in[16],         // 16-bit input
        load,           // control signal
        address[3];     // 3-bit address

    OUT out[16],        // 16-bit output
        ready;          // status signal

    PARTS:
    // Built-in chip reference
    BUILTIN ALU;

    // Clocked body
    CLOCKED DFF, Register;

    // Part instantiation with connections
    Mux16(a=in, b=out, sel=load, out=muxOut);
    
    // Register with bus connections
    Register(in=muxOut, load=load, out=out);
    
    // Complex connection
    ALU(x=in, y=out, zx=load, nx=false, zy=true, ny=false, 
        f=true, no=false, out=aluOut, zr=zero, ng=negative);
}