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32 lines
1.3 KiB
Plaintext
32 lines
1.3 KiB
Plaintext
// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/3/a/RAM64.hdl
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/**
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* Memory of sixty four 16-bit registers.
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* If load is asserted, the value of the register selected by
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* address is set to in; Otherwise, the value does not change.
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* The value of the selected register is emitted by out.
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*/
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CHIP RAM64 {
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IN in[16], load, address[6];
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OUT out[16];
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PARTS:
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// send load to correct RAM8 (high 3 bits)
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DMux8Way(in=load, sel=address[3..5], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
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// 8 RAM8 chips (low 3 bits select register within each)
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RAM8(in=in, load=load0, address=address[0..2], out=out0);
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RAM8(in=in, load=load1, address=address[0..2], out=out1);
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RAM8(in=in, load=load2, address=address[0..2], out=out2);
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RAM8(in=in, load=load3, address=address[0..2], out=out3);
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RAM8(in=in, load=load4, address=address[0..2], out=out4);
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RAM8(in=in, load=load5, address=address[0..2], out=out5);
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RAM8(in=in, load=load6, address=address[0..2], out=out6);
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RAM8(in=in, load=load7, address=address[0..2], out=out7);
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// select out from correct RAM8
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Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[3..5], out=out);
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}
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