eceg431/01

Project 1: Elementary Logic Gates

The description for this project is found at:

https://www.nand2tetris.org/project01

You may _not_ work as pairs on this project. Please work individually.

NOTES:

1) Be careful not to make a recursive part declaration. The most common way is accidentally listing the chip that is being implemented in the PARTS list. The second most common way is by using PartA, which uses PartB, which in-turn uses PartA. Oops. Implementing the chips in the recommend order will help ensure this doesn't happen.

2) The HDL language and format is described in Appendix A. One thing to note early on is that this HDL is case-sensitive.

3) There is also a HDL survival guide posted at https://www.nand2tetris.org/hdl-survival-guide

4) The book authors have a distinction between multi-bit and multi-way. Watch out that you are implementing the correct specification for these items.