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2e8ebbbfd52b87939cc817b10b8f68ce9ee4a297
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4 Commits

Author SHA1 Message Date
Sean O'Connor
2e8ebbbfd5 project02 complete, add .gitignore 2025-09-02 08:33:07 -04:00
Sean O'Connor
b0c57a8a7e Fix ALU: Use out pin directly instead of internal finalout bus 
- Removed invalid finalout internal bus
- Use out[0..7], out[8..15], out[15] directly for flag computation
- Fixes HDL sub-bus restriction error
 2025-09-01 15:03:26 -04:00
Sean O'Connor
2b3da7a171 Implement Project 2: Arithmetic Logic Unit 
✅ HalfAdder: XOR for sum, AND for carry
✅ FullAdder: Two half adders + OR
✅ Add16: Chain of 16 full adders with carry
✅ Inc16: Add16 with constant 1
✅ ALU: Complete arithmetic logic unit with all operations

Used concise, student-style comments throughout.
 2025-08-30 19:49:23 -04:00
Sean O'Connor
4563dd234b Add project 2 template files 2025-08-30 19:47:34 -04:00