From e48586826545bd77fbfc6313db1a6e31a6266b26 Mon Sep 17 00:00:00 2001
From: Sean O'Connor <sean@soconnor.dev>
Date: Wed, 3 Sep 2025 10:19:05 -0400
Subject: [PATCH] project03 - create bit, register, and program counter

---
 03/a/Bit.hdl      |  5 ++++-
 03/a/PC.hdl       | 19 +++++++++++++++++--
 03/a/Register.hdl | 18 +++++++++++++++++-
 3 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/03/a/Bit.hdl b/03/a/Bit.hdl
index bb3e4bc..3d85236 100644
--- a/03/a/Bit.hdl
+++ b/03/a/Bit.hdl
@@ -13,5 +13,8 @@ CHIP Bit {
     OUT out;
 
     PARTS:
-    //// Replace this comment with your code.
+    // choose new input or current stored value
+    Mux(a=dffOut, b=in, sel=load, out=muxOut);
+    // DFF (new): hold val
+    DFF(in=muxOut, out=out, out=dffOut);
 }
diff --git a/03/a/PC.hdl b/03/a/PC.hdl
index e4baefc..ce91ede 100644
--- a/03/a/PC.hdl
+++ b/03/a/PC.hdl
@@ -12,7 +12,22 @@
 CHIP PC {
     IN in[16],inc, load, reset;
     OUT out[16];
-    
+
     PARTS:
-    //// Replace this comment with your code.
+    // inc current value
+    Inc16(in=regOut, out=incOut);
+
+    // choose current or inc'd val (based on inc)
+    Mux16(a=regOut, b=incOut, sel=inc, out=postInc);
+    // choose ^ vs input (based on load)
+    Mux16(a=postInc, b=in, sel=load, out=postLoad);
+    // choose ^ vs zero (based on reset)
+    Mux16(a=postLoad, b=false, sel=reset, out=nextVal);
+
+    // load register if any control signal is active
+    Or(a=reset, b=load, out=resetOrLoad);
+    Or(a=resetOrLoad, b=inc, out=shouldLoad);
+
+    // stores state
+    Register(in=nextVal, load=shouldLoad, out=regOut, out=out);
 }
diff --git a/03/a/Register.hdl b/03/a/Register.hdl
index fe83442..82454bb 100644
--- a/03/a/Register.hdl
+++ b/03/a/Register.hdl
@@ -13,5 +13,21 @@ CHIP Register {
     OUT out[16];
 
     PARTS:
-    //// Replace this comment with your code.
+    // 16 bit register = 16 bits, in a register
+    Bit(in=in[0], load=load, out=out[0]);
+    Bit(in=in[1], load=load, out=out[1]);
+    Bit(in=in[2], load=load, out=out[2]);
+    Bit(in=in[3], load=load, out=out[3]);
+    Bit(in=in[4], load=load, out=out[4]);
+    Bit(in=in[5], load=load, out=out[5]);
+    Bit(in=in[6], load=load, out=out[6]);
+    Bit(in=in[7], load=load, out=out[7]);
+    Bit(in=in[8], load=load, out=out[8]);
+    Bit(in=in[9], load=load, out=out[9]);
+    Bit(in=in[10], load=load, out=out[10]);
+    Bit(in=in[11], load=load, out=out[11]);
+    Bit(in=in[12], load=load, out=out[12]);
+    Bit(in=in[13], load=load, out=out[13]);
+    Bit(in=in[14], load=load, out=out[14]);
+    Bit(in=in[15], load=load, out=out[15]);
 }