project02: Comments/cleanup

This commit is contained in:
2025-09-03 22:55:08 -04:00
parent 934f1ad2f5
commit e1c0b091a8
2 changed files with 9 additions and 6 deletions

View File

@@ -65,16 +65,16 @@ CHIP ALU {
Not16(in=fout, out=notfout); Not16(in=fout, out=notfout);
Mux16(a=fout, b=notfout, sel=no, out=out, out[0..7]=outLow, out[8..15]=outHigh, out[15]=sign); Mux16(a=fout, b=notfout, sel=no, out=out, out[0..7]=outLow, out[8..15]=outHigh, out[15]=sign);
// compute zr (zero flag) // compute zr (zero flag): set if output is all zeros
// check if any bits in low 8 are set // check if any bits in low 8 are set
Or8Way(in=outLow, out=tmp1); Or8Way(in=outLow, out=lowOnes);
// check if any bits in high 8 are set // check if any bits in high 8 are set
Or8Way(in=outHigh, out=tmp2); Or8Way(in=outHigh, out=highOnes);
// combine both halves (true if any bit is set) // combine both halves (true if any bit is set)
Or(a=tmp1, b=tmp2, out=notzr); Or(a=lowOnes, b=highOnes, out=notzr);
// zr = true if no bits are set (output is zero) // zr set if no bits are set (output is zero)
Not(in=notzr, out=zr); Not(in=notzr, out=zr);
// compute ng (negative flag) // compute ng (negative flag): set if leftmost bit is 1 (two's complement)
And(a=sign, b=true, out=ng); And(a=sign, b=true, out=ng);
} }

View File

@@ -11,7 +11,10 @@ CHIP FullAdder {
carry; // Left bit of a + b + c carry; // Left bit of a + b + c
PARTS: PARTS:
// add first two inputs
HalfAdder(a=a, b=b, sum=absum, carry=c0); HalfAdder(a=a, b=b, sum=absum, carry=c0);
// add third input to partial sum
HalfAdder(a=absum, b=c, sum=sum, carry=c1); HalfAdder(a=absum, b=c, sum=sum, carry=c1);
// combine both carry bits
Or(a=c0, b=c1, out=carry); Or(a=c0, b=c1, out=carry);
} }