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project03: Compound RAM chips

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This commit is contained in:
Sean O'Connor
2025-09-03 10:45:00 -04:00
parent e485868265
commit d0c67845f4
5 changed files with 71 additions and 5 deletions
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16
03/a/RAM64.hdl
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@@ -13,5 +13,19 @@ CHIP RAM64 {
OUT out[16];
PARTS:
//// Replace this comment with your code.
// find which RAM8 to load by address (from high three bits)
DMux8Way(in=load, sel=address[3..5], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
// 8 RAM8 chips (low 3 bits select register within each)
RAM8(in=in, load=load0, address=address[0..2], out=out0);
RAM8(in=in, load=load1, address=address[0..2], out=out1);
RAM8(in=in, load=load2, address=address[0..2], out=out2);
RAM8(in=in, load=load3, address=address[0..2], out=out3);
RAM8(in=in, load=load4, address=address[0..2], out=out4);
RAM8(in=in, load=load5, address=address[0..2], out=out5);
RAM8(in=in, load=load6, address=address[0..2], out=out6);
RAM8(in=in, load=load7, address=address[0..2], out=out7);
// select which RAM8 output to send
Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[3..5], out=out);
}

16
03/a/RAM8.hdl
View File

@@ -13,5 +13,19 @@ CHIP RAM8 {
OUT out[16];
PARTS:
//// Replace this comment with your code.
// find which register to load by address
DMux8Way(in=load, sel=address, a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
// 8 registers to store data
Register(in=in, load=load0, out=out0);
Register(in=in, load=load1, out=out1);
Register(in=in, load=load2, out=out2);
Register(in=in, load=load3, out=out3);
Register(in=in, load=load4, out=out4);
Register(in=in, load=load5, out=out5);
Register(in=in, load=load6, out=out6);
Register(in=in, load=load7, out=out7);
// select which registers output to send
Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address, out=out);
}

12
03/b/RAM16K.hdl
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@@ -13,5 +13,15 @@ CHIP RAM16K {
OUT out[16];
PARTS:
//// Replace this comment with your code.
// find which RAM4K to load by address (from high two bits)
DMux4Way(in=load, sel=address[12..13], a=load0, b=load1, c=load2, d=load3);
// 4 RAM4K chips (low 12 bits select register within each)
RAM4K(in=in, load=load0, address=address[0..11], out=out0);
RAM4K(in=in, load=load1, address=address[0..11], out=out1);
RAM4K(in=in, load=load2, address=address[0..11], out=out2);
RAM4K(in=in, load=load3, address=address[0..11], out=out3);
// select which RAM4K output to send
Mux4Way16(a=out0, b=out1, c=out2, d=out3, sel=address[12..13], out=out);
}

16
03/b/RAM4K.hdl
View File

@@ -13,5 +13,19 @@ CHIP RAM4K {
OUT out[16];
PARTS:
//// Replace this comment with your code.
// find which RAM512 to load by address (from high three bits)
DMux8Way(in=load, sel=address[9..11], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
// 8 RAM512 chips (low 9 bits select register within each)
RAM512(in=in, load=load0, address=address[0..8], out=out0);
RAM512(in=in, load=load1, address=address[0..8], out=out1);
RAM512(in=in, load=load2, address=address[0..8], out=out2);
RAM512(in=in, load=load3, address=address[0..8], out=out3);
RAM512(in=in, load=load4, address=address[0..8], out=out4);
RAM512(in=in, load=load5, address=address[0..8], out=out5);
RAM512(in=in, load=load6, address=address[0..8], out=out6);
RAM512(in=in, load=load7, address=address[0..8], out=out7);
// select which RAM512 output to send
Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[9..11], out=out);
}

16
03/b/RAM512.hdl
View File

@@ -13,5 +13,19 @@ CHIP RAM512 {
OUT out[16];
PARTS:
//// Replace this comment with your code.
// find which RAM64 to load by address (from high three bits)
DMux8Way(in=load, sel=address[6..8], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
// 8 RAM64 chips (low 6 bits select register within each)
RAM64(in=in, load=load0, address=address[0..5], out=out0);
RAM64(in=in, load=load1, address=address[0..5], out=out1);
RAM64(in=in, load=load2, address=address[0..5], out=out2);
RAM64(in=in, load=load3, address=address[0..5], out=out3);
RAM64(in=in, load=load4, address=address[0..5], out=out4);
RAM64(in=in, load=load5, address=address[0..5], out=out5);
RAM64(in=in, load=load6, address=address[0..5], out=out6);
RAM64(in=in, load=load7, address=address[0..5], out=out7);
// select which RAM64 output to send
Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[6..8], out=out);
}