From c39ce212b4f79decc1582e902ccd247e74e0bacf Mon Sep 17 00:00:00 2001 From: Sean O'Connor Date: Thu, 28 Aug 2025 15:11:48 +0200 Subject: [PATCH] Simplify comments to be more concise and student-like - Removed verbose explanations - Made comments shorter and more casual - Focus on key concepts rather than formal descriptions --- 01/And.hdl | 2 +- 01/And16.hdl | 2 +- 01/DMux.hdl | 2 +- 01/DMux4Way.hdl | 2 +- 01/DMux8Way.hdl | 2 +- 01/Mux.hdl | 2 +- 01/Mux16.hdl | 2 +- 01/Mux4Way16.hdl | 2 +- 01/Mux8Way16.hdl | 2 +- 01/Not.hdl | 2 +- 01/Not16.hdl | 2 +- 01/Or.hdl | 2 +- 01/Or16.hdl | 2 +- 01/Or8Way.hdl | 2 +- 01/Xor.hdl | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/01/And.hdl b/01/And.hdl index 66dbab6..ada4be7 100644 --- a/01/And.hdl +++ b/01/And.hdl @@ -11,7 +11,7 @@ CHIP And { OUT out; PARTS: - // And(a,b) = Not(Nand(a,b)) + // And = Not(Nand) Nand(a=a, b=b, out=tmp); Not(in=tmp, out=out); } diff --git a/01/And16.hdl b/01/And16.hdl index 1e0884a..6a4d3a4 100644 --- a/01/And16.hdl +++ b/01/And16.hdl @@ -12,7 +12,7 @@ CHIP And16 { OUT out[16]; PARTS: - // Apply And gate to each of the 16 bits + // And each bit And(a=a[0], b=b[0], out=out[0]); And(a=a[1], b=b[1], out=out[1]); And(a=a[2], b=b[2], out=out[2]); diff --git a/01/DMux.hdl b/01/DMux.hdl index ae96914..99997a9 100644 --- a/01/DMux.hdl +++ b/01/DMux.hdl @@ -12,7 +12,7 @@ CHIP DMux { OUT a, b; PARTS: - // DMux(in,sel) -> a = And(in, Not(sel)), b = And(in, sel) + // sel=0 sends to a, sel=1 sends to b Not(in=sel, out=tmp); And(a=in, b=tmp, out=a); And(a=in, b=sel, out=b); diff --git a/01/DMux4Way.hdl b/01/DMux4Way.hdl index b95014e..b105867 100644 --- a/01/DMux4Way.hdl +++ b/01/DMux4Way.hdl @@ -14,7 +14,7 @@ CHIP DMux4Way { OUT a, b, c, d; PARTS: - // Use two levels of DMux: first level splits by sel[1], second level splits by sel[0] + // Two levels of DMux DMux(in=in, sel=sel[1], a=tmp1, b=tmp2); DMux(in=tmp1, sel=sel[0], a=a, b=b); DMux(in=tmp2, sel=sel[0], a=c, b=d); diff --git a/01/DMux8Way.hdl b/01/DMux8Way.hdl index d655b6c..7bb487e 100644 --- a/01/DMux8Way.hdl +++ b/01/DMux8Way.hdl @@ -18,7 +18,7 @@ CHIP DMux8Way { OUT a, b, c, d, e, f, g, h; PARTS: - // Use one DMux and two DMux4Way gates: first split by sel[2], then each half by sel[0..1] + // One DMux + two DMux4Way DMux(in=in, sel=sel[2], a=tmp1, b=tmp2); DMux4Way(in=tmp1, sel=sel[0..1], a=a, b=b, c=c, d=d); DMux4Way(in=tmp2, sel=sel[0..1], a=e, b=f, c=g, d=h); diff --git a/01/Mux.hdl b/01/Mux.hdl index a6ed658..491f694 100644 --- a/01/Mux.hdl +++ b/01/Mux.hdl @@ -11,7 +11,7 @@ CHIP Mux { OUT out; PARTS: - // Mux(a,b,sel) = Or(And(a, Not(sel)), And(b, sel)) + // sel=0 picks a, sel=1 picks b Not(in=sel, out=tmp1); And(a=a, b=tmp1, out=tmp2); And(a=b, b=sel, out=tmp3); diff --git a/01/Mux16.hdl b/01/Mux16.hdl index 950af3b..f44b4b9 100644 --- a/01/Mux16.hdl +++ b/01/Mux16.hdl @@ -12,7 +12,7 @@ CHIP Mux16 { OUT out[16]; PARTS: - // Apply Mux gate to each of the 16 bits + // Mux each bit Mux(a=a[0], b=b[0], sel=sel, out=out[0]); Mux(a=a[1], b=b[1], sel=sel, out=out[1]); Mux(a=a[2], b=b[2], sel=sel, out=out[2]); diff --git a/01/Mux4Way16.hdl b/01/Mux4Way16.hdl index 8fd6032..b217e73 100644 --- a/01/Mux4Way16.hdl +++ b/01/Mux4Way16.hdl @@ -14,7 +14,7 @@ CHIP Mux4Way16 { OUT out[16]; PARTS: - // Use two levels of Mux16: first level selects between pairs, second level selects final output + // Two levels of Mux16 Mux16(a=a, b=b, sel=sel[0], out=tmp1); Mux16(a=c, b=d, sel=sel[0], out=tmp2); Mux16(a=tmp1, b=tmp2, sel=sel[1], out=out); diff --git a/01/Mux8Way16.hdl b/01/Mux8Way16.hdl index a2f9201..57b73f4 100644 --- a/01/Mux8Way16.hdl +++ b/01/Mux8Way16.hdl @@ -20,7 +20,7 @@ CHIP Mux8Way16 { OUT out[16]; PARTS: - // Use two Mux4Way16 gates and one Mux16 to select from 8 inputs + // Two Mux4Way16 + one Mux16 Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=tmp1); Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=tmp2); Mux16(a=tmp1, b=tmp2, sel=sel[2], out=out); diff --git a/01/Not.hdl b/01/Not.hdl index 7924706..049ff67 100644 --- a/01/Not.hdl +++ b/01/Not.hdl @@ -11,6 +11,6 @@ CHIP Not { OUT out; PARTS: - // Not(in) = Nand(in, in) + // Not = Nand with same input Nand(a=in, b=in, out=out); } diff --git a/01/Not16.hdl b/01/Not16.hdl index 0d8c5a1..3f74e4e 100644 --- a/01/Not16.hdl +++ b/01/Not16.hdl @@ -12,7 +12,7 @@ CHIP Not16 { OUT out[16]; PARTS: - // Apply Not gate to each of the 16 bits + // Not each bit Not(in=in[0], out=out[0]); Not(in=in[1], out=out[1]); Not(in=in[2], out=out[2]); diff --git a/01/Or.hdl b/01/Or.hdl index 4574574..7b8e87c 100644 --- a/01/Or.hdl +++ b/01/Or.hdl @@ -11,7 +11,7 @@ CHIP Or { OUT out; PARTS: - // Or(a,b) = Not(And(Not(a), Not(b))) - De Morgan's law + // De Morgan's law Not(in=a, out=tmp1); Not(in=b, out=tmp2); And(a=tmp1, b=tmp2, out=tmp3); diff --git a/01/Or16.hdl b/01/Or16.hdl index 7e6556c..72dfb80 100644 --- a/01/Or16.hdl +++ b/01/Or16.hdl @@ -12,7 +12,7 @@ CHIP Or16 { OUT out[16]; PARTS: - // Apply Or gate to each of the 16 bits + // Or each bit Or(a=a[0], b=b[0], out=out[0]); Or(a=a[1], b=b[1], out=out[1]); Or(a=a[2], b=b[2], out=out[2]); diff --git a/01/Or8Way.hdl b/01/Or8Way.hdl index 35f0d34..3cfe6bb 100644 --- a/01/Or8Way.hdl +++ b/01/Or8Way.hdl @@ -11,7 +11,7 @@ CHIP Or8Way { OUT out; PARTS: - // Chain Or gates to combine all 8 inputs + // Chain Or gates Or(a=in[0], b=in[1], out=tmp1); Or(a=in[2], b=in[3], out=tmp2); Or(a=in[4], b=in[5], out=tmp3); diff --git a/01/Xor.hdl b/01/Xor.hdl index ecaa0f9..1723bcb 100644 --- a/01/Xor.hdl +++ b/01/Xor.hdl @@ -11,7 +11,7 @@ CHIP Xor { OUT out; PARTS: - // Xor(a,b) = Or(And(a, Not(b)), And(Not(a), b)) + // Xor = (a AND !b) OR (!a AND b) Not(in=a, out=tmp1); Not(in=b, out=tmp2); And(a=a, b=tmp2, out=tmp3);