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add project03 base files

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This commit is contained in:
Sean O'Connor
2025-09-02 08:33:16 -04:00
parent 2e8ebbbfd5
commit c2cea97f87
16 changed files with 6361 additions and 0 deletions
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17
03/a/Bit.hdl Normal file
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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/Bit.hdl
/**
* 1-bit register:
* If load is asserted, the register's value is set to in;
* Otherwise, the register maintains its current value:
* if (load(t)) out(t+1) = in(t), else out(t+1) = out(t)
*/
CHIP Bit {
IN in, load;
OUT out;
PARTS:
//// Replace this comment with your code.
}

865
03/a/Bit.tst Normal file
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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/Bit.tst
load Bit.hdl,
output-file Bit.out,
compare-to Bit.cmp,
output-list time%S1.4.1 in load%B1.1.2 out;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 1,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in 1,
set load 1,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;

18
03/a/PC.hdl Normal file
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@@ -0,0 +1,18 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/PC.hdl
/**
* A 16-bit counter.
* if reset(t): out(t+1) = 0
* else if load(t): out(t+1) = in(t)
* else if inc(t): out(t+1) = out(t) + 1
* else out(t+1) = out(t)
*/
CHIP PC {
IN in[16],inc, load, reset;
OUT out[16];
PARTS:
//// Replace this comment with your code.
}

125
03/a/PC.tst Normal file
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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.tst
load PC.hdl,
output-file PC.out,
compare-to PC.cmp,
output-list time%S1.3.1 in%D1.6.1 reset%B2.1.2 load%B2.1.2 inc%B2.1.2 out%D1.6.1;
set in 0,
set reset 0,
set load 0,
set inc 0,
tick,
output;
tock,
output;
set inc 1,
tick,
output;
tock,
output;
set in -32123,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set load 0,
tick,
output;
tock,
output;
tick,
output;
tock,
output;
set in 12345,
set load 1,
set inc 0,
tick,
output;
tock,
output;
set reset 1,
tick,
output;
tock,
output;
set reset 0,
set inc 1,
tick,
output;
tock,
output;
set reset 1,
tick,
output;
tock,
output;
set reset 0,
set load 0,
tick,
output;
tock,
output;
set reset 1,
tick,
output;
tock,
output;
set in 0,
set reset 0,
set load 1,
tick,
output;
tock,
output;
set load 0,
set inc 1,
tick,
output;
tock,
output;
set in 22222,
set reset 1,
set inc 0,
tick,
output;
tock,
output;

17
03/a/RAM64.hdl Normal file
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@@ -0,0 +1,17 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/RAM64.hdl
/**
* Memory of sixty four 16-bit registers.
* If load is asserted, the value of the register selected by
* address is set to in; Otherwise, the value does not change.
* The value of the selected register is emitted by out.
*/
CHIP RAM64 {
IN in[16], load, address[6];
OUT out[16];
PARTS:
//// Replace this comment with your code.
}

1026
03/a/RAM64.tst Normal file
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File diff suppressed because it is too large Load Diff

17
03/a/RAM8.hdl Normal file
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@@ -0,0 +1,17 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/RAM8.hdl
/**
* Memory of eight 16-bit registers.
* If load is asserted, the value of the register selected by
* address is set to in; Otherwise, the value does not change.
* The value of the selected register is emitted by out.
*/
CHIP RAM8 {
IN in[16], load, address[3];
OUT out[16];
PARTS:
//// Replace this comment with your code.
}

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03/a/RAM8.tst Normal file
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@@ -0,0 +1,560 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/RAM8.tst
load RAM8.hdl,
output-file RAM8.out,
compare-to RAM8.cmp,
output-list time%S1.3.1 in%D1.6.1 load%B2.1.1 address%D3.1.3 out%D1.6.1;
set in 0,
set load 0,
set address 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in 11111,
set load 0,
tick,
output;
tock,
output;
set load 1,
set address 1,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set in 3333,
set address 3,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set load 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set in 7777,
tick,
output;
tock,
output;
set load 1,
set address 7,
tick,
output;
tock,
output;
set load 0,
tick,
output;
tock,
output;
set address 3,
eval,
output;
set address 7,
eval,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set in %B0101010101010101,
set address 0,
tick,
output;
tock,
output;
set address 1,
tick,
output,
tock,
output;
set address 2,
tick,
output,
tock,
output;
set address 3,
tick,
output,
tock,
output;
set address 4,
tick,
output,
tock,
output;
set address 5,
tick,
output,
tock,
output;
set address 6,
tick,
output,
tock,
output;
set address 7,
tick,
output,
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 0,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 0,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 1,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 1,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 2,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 2,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 3,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 3,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 4,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 4,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 5,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 5,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 6,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 6,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 7,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 7,
set in %B0101010101010101,
tick,
output,
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;

17
03/a/Register.hdl Normal file
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@@ -0,0 +1,17 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/Register.hdl
/**
* 16-bit register:
* If load is asserted, the register's value is set to in;
* Otherwise, the register maintains its current value:
* if (load(t)) out(t+1) = int(t), else out(t+1) = out(t)
*/
CHIP Register {
IN in[16], load;
OUT out[16];
PARTS:
//// Replace this comment with your code.
}

569
03/a/Register.tst Normal file
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@@ -0,0 +1,569 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/a/Register.tst
load Register.hdl,
output-file Register.out,
compare-to Register.cmp,
output-list time%S1.3.1 in%D1.6.1 load%B2.1.1 out%D1.6.1;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in -32123,
set load 0,
tick,
output;
tock,
output;
set in 11111,
set load 0,
tick,
output;
tock,
output;
set in -32123,
set load 1,
tick,
output;
tock,
output;
set in -32123,
set load 1,
tick,
output;
tock,
output;
set in -32123,
set load 0,
tick,
output;
tock,
output;
set in 12345,
set load 1,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in %B0000000000000001,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000000010,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000000100,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000001000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000010000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000100000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000001000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000010000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000100000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000001000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000010000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000100000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0001000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0010000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0100000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1000000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111111110,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111111101,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111111011,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111110111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111101111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111011111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111110111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111101111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111011111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111110111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111101111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111011111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1110111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1101111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1011111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0111111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;

17
03/b/RAM16K.hdl Normal file
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@@ -0,0 +1,17 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/b/RAM16K.hdl
/**
* Memory of 16K 16-bit registers.
* If load is asserted, the value of the register selected by
* address is set to in; Otherwise, the value does not change.
* The value of the selected register is emitted by out.
*/
CHIP RAM16K {
IN in[16], load, address[14];
OUT out[16];
PARTS:
//// Replace this comment with your code.
}

1026
03/b/RAM16K.tst Normal file
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17
03/b/RAM4K.hdl Normal file
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@@ -0,0 +1,17 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/b/RAM4K.hdl
/**
* Memory of 4K 16-bit registers.
* If load is asserted, the value of the register selected by
* address is set to in; Otherwise, the value does not change.
* The value of the selected register is emitted by out.
*/
CHIP RAM4K {
IN in[16], load, address[12];
OUT out[16];
PARTS:
//// Replace this comment with your code.
}

1026
03/b/RAM4K.tst Normal file
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17
03/b/RAM512.hdl Normal file
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@@ -0,0 +1,17 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/3/b/RAM512.hdl
/**
* Memory of 512 16-bit registers.
* If load is asserted, the value of the register selected by
* address is set to in; Otherwise, the value does not change.
* The value of the selected register is emitted by out.
*/
CHIP RAM512 {
IN in[16], load, address[9];
OUT out[16];
PARTS:
//// Replace this comment with your code.
}

1027
03/b/RAM512.tst Normal file
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