From 93f730d0cec047a7012eebdc2f1b65ff7d6a7823 Mon Sep 17 00:00:00 2001
From: Sean O'Connor <sean@soconnor.dev>
Date: Wed, 27 Aug 2025 19:08:17 +0200
Subject: [PATCH] Implement 16-bit logic gates: Not16, And16, Or16, Mux16

---
 01/And16.hdl | 22 +++++++++++++++++++---
 01/Mux16.hdl | 20 ++++++++++++++++++--
 01/Not16.hdl | 20 ++++++++++++++++++--
 01/Or16.hdl  | 22 +++++++++++++++++++---
 4 files changed, 74 insertions(+), 10 deletions(-)

diff --git a/01/And16.hdl b/01/And16.hdl
index dfd56bc..1e0884a 100644
--- a/01/And16.hdl
+++ b/01/And16.hdl
@@ -5,12 +5,28 @@
 /**
  * 16-bit And gate:
  * for i = 0, ..., 15:
- * out[i] = a[i] And b[i] 
+ * out[i] = a[i] And b[i]
  */
 CHIP And16 {
     IN a[16], b[16];
     OUT out[16];
 
     PARTS:
-    //// Replace this comment with your code.
-}
\ No newline at end of file
+    // Apply And gate to each of the 16 bits
+    And(a=a[0], b=b[0], out=out[0]);
+    And(a=a[1], b=b[1], out=out[1]);
+    And(a=a[2], b=b[2], out=out[2]);
+    And(a=a[3], b=b[3], out=out[3]);
+    And(a=a[4], b=b[4], out=out[4]);
+    And(a=a[5], b=b[5], out=out[5]);
+    And(a=a[6], b=b[6], out=out[6]);
+    And(a=a[7], b=b[7], out=out[7]);
+    And(a=a[8], b=b[8], out=out[8]);
+    And(a=a[9], b=b[9], out=out[9]);
+    And(a=a[10], b=b[10], out=out[10]);
+    And(a=a[11], b=b[11], out=out[11]);
+    And(a=a[12], b=b[12], out=out[12]);
+    And(a=a[13], b=b[13], out=out[13]);
+    And(a=a[14], b=b[14], out=out[14]);
+    And(a=a[15], b=b[15], out=out[15]);
+}
diff --git a/01/Mux16.hdl b/01/Mux16.hdl
index 3d2bccf..950af3b 100644
--- a/01/Mux16.hdl
+++ b/01/Mux16.hdl
@@ -3,7 +3,7 @@
 // by Nisan and Schocken, MIT Press.
 // File name: projects/1/Mux16.hdl
 /**
- * 16-bit multiplexor: 
+ * 16-bit multiplexor:
  * for i = 0, ..., 15:
  * if (sel = 0) out[i] = a[i], else out[i] = b[i]
  */
@@ -12,5 +12,21 @@ CHIP Mux16 {
     OUT out[16];
 
     PARTS:
-    //// Replace this comment with your code.
+    // Apply Mux gate to each of the 16 bits
+    Mux(a=a[0], b=b[0], sel=sel, out=out[0]);
+    Mux(a=a[1], b=b[1], sel=sel, out=out[1]);
+    Mux(a=a[2], b=b[2], sel=sel, out=out[2]);
+    Mux(a=a[3], b=b[3], sel=sel, out=out[3]);
+    Mux(a=a[4], b=b[4], sel=sel, out=out[4]);
+    Mux(a=a[5], b=b[5], sel=sel, out=out[5]);
+    Mux(a=a[6], b=b[6], sel=sel, out=out[6]);
+    Mux(a=a[7], b=b[7], sel=sel, out=out[7]);
+    Mux(a=a[8], b=b[8], sel=sel, out=out[8]);
+    Mux(a=a[9], b=b[9], sel=sel, out=out[9]);
+    Mux(a=a[10], b=b[10], sel=sel, out=out[10]);
+    Mux(a=a[11], b=b[11], sel=sel, out=out[11]);
+    Mux(a=a[12], b=b[12], sel=sel, out=out[12]);
+    Mux(a=a[13], b=b[13], sel=sel, out=out[13]);
+    Mux(a=a[14], b=b[14], sel=sel, out=out[14]);
+    Mux(a=a[15], b=b[15], sel=sel, out=out[15]);
 }
diff --git a/01/Not16.hdl b/01/Not16.hdl
index e88babf..0d8c5a1 100644
--- a/01/Not16.hdl
+++ b/01/Not16.hdl
@@ -12,5 +12,21 @@ CHIP Not16 {
     OUT out[16];
 
     PARTS:
-    //// Replace this comment with your code.
-}
\ No newline at end of file
+    // Apply Not gate to each of the 16 bits
+    Not(in=in[0], out=out[0]);
+    Not(in=in[1], out=out[1]);
+    Not(in=in[2], out=out[2]);
+    Not(in=in[3], out=out[3]);
+    Not(in=in[4], out=out[4]);
+    Not(in=in[5], out=out[5]);
+    Not(in=in[6], out=out[6]);
+    Not(in=in[7], out=out[7]);
+    Not(in=in[8], out=out[8]);
+    Not(in=in[9], out=out[9]);
+    Not(in=in[10], out=out[10]);
+    Not(in=in[11], out=out[11]);
+    Not(in=in[12], out=out[12]);
+    Not(in=in[13], out=out[13]);
+    Not(in=in[14], out=out[14]);
+    Not(in=in[15], out=out[15]);
+}
diff --git a/01/Or16.hdl b/01/Or16.hdl
index 4337602..7e6556c 100644
--- a/01/Or16.hdl
+++ b/01/Or16.hdl
@@ -5,12 +5,28 @@
 /**
  * 16-bit Or gate:
  * for i = 0, ..., 15:
- * out[i] = a[i] Or b[i] 
+ * out[i] = a[i] Or b[i]
  */
 CHIP Or16 {
     IN a[16], b[16];
     OUT out[16];
 
     PARTS:
-    //// Replace this comment with your code.
-}
\ No newline at end of file
+    // Apply Or gate to each of the 16 bits
+    Or(a=a[0], b=b[0], out=out[0]);
+    Or(a=a[1], b=b[1], out=out[1]);
+    Or(a=a[2], b=b[2], out=out[2]);
+    Or(a=a[3], b=b[3], out=out[3]);
+    Or(a=a[4], b=b[4], out=out[4]);
+    Or(a=a[5], b=b[5], out=out[5]);
+    Or(a=a[6], b=b[6], out=out[6]);
+    Or(a=a[7], b=b[7], out=out[7]);
+    Or(a=a[8], b=b[8], out=out[8]);
+    Or(a=a[9], b=b[9], out=out[9]);
+    Or(a=a[10], b=b[10], out=out[10]);
+    Or(a=a[11], b=b[11], out=out[11]);
+    Or(a=a[12], b=b[12], out=out[12]);
+    Or(a=a[13], b=b[13], out=out[13]);
+    Or(a=a[14], b=b[14], out=out[14]);
+    Or(a=a[15], b=b[15], out=out[15]);
+}