mirror of
https://github.com/soconnor0919/eceg431.git
synced 2025-12-11 22:54:43 -05:00
Implement multi-way gates: Or8Way, Mux4Way16, Mux8Way16, DMux4Way, DMux8Way
This commit is contained in:
@@ -14,5 +14,8 @@ CHIP DMux4Way {
|
|||||||
OUT a, b, c, d;
|
OUT a, b, c, d;
|
||||||
|
|
||||||
PARTS:
|
PARTS:
|
||||||
//// Replace this comment with your code.
|
// Use two levels of DMux: first level splits by sel[1], second level splits by sel[0]
|
||||||
}
|
DMux(in=in, sel=sel[1], a=dmuxAB, b=dmuxCD);
|
||||||
|
DMux(in=dmuxAB, sel=sel[0], a=a, b=b);
|
||||||
|
DMux(in=dmuxCD, sel=sel[0], a=c, b=d);
|
||||||
|
}
|
||||||
|
|||||||
@@ -18,5 +18,8 @@ CHIP DMux8Way {
|
|||||||
OUT a, b, c, d, e, f, g, h;
|
OUT a, b, c, d, e, f, g, h;
|
||||||
|
|
||||||
PARTS:
|
PARTS:
|
||||||
//// Replace this comment with your code.
|
// Use one DMux and two DMux4Way gates: first split by sel[2], then each half by sel[0..1]
|
||||||
|
DMux(in=in, sel=sel[2], a=dmuxABCD, b=dmuxEFGH);
|
||||||
|
DMux4Way(in=dmuxABCD, sel=sel[0..1], a=a, b=b, c=c, d=d);
|
||||||
|
DMux4Way(in=dmuxEFGH, sel=sel[0..1], a=e, b=f, c=g, d=h);
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -12,7 +12,10 @@
|
|||||||
CHIP Mux4Way16 {
|
CHIP Mux4Way16 {
|
||||||
IN a[16], b[16], c[16], d[16], sel[2];
|
IN a[16], b[16], c[16], d[16], sel[2];
|
||||||
OUT out[16];
|
OUT out[16];
|
||||||
|
|
||||||
PARTS:
|
PARTS:
|
||||||
//// Replace this comment with your code.
|
// Use two levels of Mux16: first level selects between pairs, second level selects final output
|
||||||
}
|
Mux16(a=a, b=b, sel=sel[0], out=muxAB);
|
||||||
|
Mux16(a=c, b=d, sel=sel[0], out=muxCD);
|
||||||
|
Mux16(a=muxAB, b=muxCD, sel=sel[1], out=out);
|
||||||
|
}
|
||||||
|
|||||||
@@ -20,5 +20,8 @@ CHIP Mux8Way16 {
|
|||||||
OUT out[16];
|
OUT out[16];
|
||||||
|
|
||||||
PARTS:
|
PARTS:
|
||||||
//// Replace this comment with your code.
|
// Use two Mux4Way16 gates and one Mux16 to select from 8 inputs
|
||||||
|
Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=mux4wayABCD);
|
||||||
|
Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=mux4wayEFGH);
|
||||||
|
Mux16(a=mux4wayABCD, b=mux4wayEFGH, sel=sel[2], out=out);
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -3,7 +3,7 @@
|
|||||||
// by Nisan and Schocken, MIT Press.
|
// by Nisan and Schocken, MIT Press.
|
||||||
// File name: projects/1/Or8Way.hdl
|
// File name: projects/1/Or8Way.hdl
|
||||||
/**
|
/**
|
||||||
* 8-way Or gate:
|
* 8-way Or gate:
|
||||||
* out = in[0] Or in[1] Or ... Or in[7]
|
* out = in[0] Or in[1] Or ... Or in[7]
|
||||||
*/
|
*/
|
||||||
CHIP Or8Way {
|
CHIP Or8Way {
|
||||||
@@ -11,5 +11,12 @@ CHIP Or8Way {
|
|||||||
OUT out;
|
OUT out;
|
||||||
|
|
||||||
PARTS:
|
PARTS:
|
||||||
//// Replace this comment with your code.
|
// Chain Or gates to combine all 8 inputs
|
||||||
}
|
Or(a=in[0], b=in[1], out=or01);
|
||||||
|
Or(a=in[2], b=in[3], out=or23);
|
||||||
|
Or(a=in[4], b=in[5], out=or45);
|
||||||
|
Or(a=in[6], b=in[7], out=or67);
|
||||||
|
Or(a=or01, b=or23, out=or0123);
|
||||||
|
Or(a=or45, b=or67, out=or4567);
|
||||||
|
Or(a=or0123, b=or4567, out=out);
|
||||||
|
}
|
||||||
|
|||||||
Reference in New Issue
Block a user