From 2b3da7a1717dac2c568784e1b0a5547f95ee4cab Mon Sep 17 00:00:00 2001
From: Sean O'Connor <sean@soconnor.dev>
Date: Sat, 30 Aug 2025 19:49:23 -0400
Subject: [PATCH] Implement Project 2: Arithmetic Logic Unit
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✅ HalfAdder: XOR for sum, AND for carry
✅ FullAdder: Two half adders + OR
✅ Add16: Chain of 16 full adders with carry
✅ Inc16: Add16 with constant 1
✅ ALU: Complete arithmetic logic unit with all operations

Used concise, student-style comments throughout.
---
 02/ALU.hdl       | 40 +++++++++++++++++++++++++++++++++++-----
 02/Add16.hdl     | 20 ++++++++++++++++++--
 02/FullAdder.hdl |  7 +++++--
 02/HalfAdder.hdl |  6 ++++--
 02/Inc16.hdl     |  5 +++--
 5 files changed, 65 insertions(+), 13 deletions(-)

diff --git a/02/ALU.hdl b/02/ALU.hdl
index 0258077..ae29ef6 100644
--- a/02/ALU.hdl
+++ b/02/ALU.hdl
@@ -27,19 +27,49 @@
 // if (no == 1) sets out = !out   // bitwise not
 
 CHIP ALU {
-    IN  
-        x[16], y[16],  // 16-bit inputs        
+    IN
+        x[16], y[16],  // 16-bit inputs
         zx, // zero the x input?
         nx, // negate the x input?
         zy, // zero the y input?
         ny, // negate the y input?
         f,  // compute (out = x + y) or (out = x & y)?
         no; // negate the out output?
-    OUT 
+    OUT
         out[16], // 16-bit output
         zr,      // if (out == 0) equals 1, else 0
         ng;      // if (out < 0)  equals 1, else 0
 
     PARTS:
-    //// Replace this comment with your code.
-}
\ No newline at end of file
+    // Step 1: Handle zx (zero x)
+    Mux16(a=x, b=false, sel=zx, out=x1);
+
+    // Step 2: Handle nx (negate x)
+    Not16(in=x1, out=notx1);
+    Mux16(a=x1, b=notx1, sel=nx, out=x2);
+
+    // Step 3: Handle zy (zero y)
+    Mux16(a=y, b=false, sel=zy, out=y1);
+
+    // Step 4: Handle ny (negate y)
+    Not16(in=y1, out=noty1);
+    Mux16(a=y1, b=noty1, sel=ny, out=y2);
+
+    // Step 5: Handle f (function: add or and)
+    Add16(a=x2, b=y2, out=addout);
+    And16(a=x2, b=y2, out=andout);
+    Mux16(a=andout, b=addout, sel=f, out=fout);
+
+    // Step 6: Handle no (negate output)
+    Not16(in=fout, out=notfout);
+    Mux16(a=fout, b=notfout, sel=no, out=out, out=finalout);
+
+    // Step 7: Compute zr (zero flag)
+    Or8Way(in=finalout[0..7], out=tmp1);
+    Or8Way(in=finalout[8..15], out=tmp2);
+    Or(a=tmp1, b=tmp2, out=notzr);
+    Not(in=notzr, out=zr);
+
+    // Step 8: Compute ng (negative flag)
+    And(a=finalout[15], b=true, out=ng);
+}
diff --git a/02/Add16.hdl b/02/Add16.hdl
index f7609bf..d4440f8 100644
--- a/02/Add16.hdl
+++ b/02/Add16.hdl
@@ -11,5 +11,21 @@ CHIP Add16 {
     OUT out[16];
 
     PARTS:
-    //// Replace this comment with your code.
-}
\ No newline at end of file
+    // Chain 16 FullAdders with carry propagation
+    HalfAdder(a=a[0], b=b[0], sum=out[0], carry=c0);
+    FullAdder(a=a[1], b=b[1], c=c0, sum=out[1], carry=c1);
+    FullAdder(a=a[2], b=b[2], c=c1, sum=out[2], carry=c2);
+    FullAdder(a=a[3], b=b[3], c=c2, sum=out[3], carry=c3);
+    FullAdder(a=a[4], b=b[4], c=c3, sum=out[4], carry=c4);
+    FullAdder(a=a[5], b=b[5], c=c4, sum=out[5], carry=c5);
+    FullAdder(a=a[6], b=b[6], c=c5, sum=out[6], carry=c6);
+    FullAdder(a=a[7], b=b[7], c=c6, sum=out[7], carry=c7);
+    FullAdder(a=a[8], b=b[8], c=c7, sum=out[8], carry=c8);
+    FullAdder(a=a[9], b=b[9], c=c8, sum=out[9], carry=c9);
+    FullAdder(a=a[10], b=b[10], c=c9, sum=out[10], carry=c10);
+    FullAdder(a=a[11], b=b[11], c=c10, sum=out[11], carry=c11);
+    FullAdder(a=a[12], b=b[12], c=c11, sum=out[12], carry=c12);
+    FullAdder(a=a[13], b=b[13], c=c12, sum=out[13], carry=c13);
+    FullAdder(a=a[14], b=b[14], c=c13, sum=out[14], carry=c14);
+    FullAdder(a=a[15], b=b[15], c=c14, sum=out[15], carry=c15);
+}
diff --git a/02/FullAdder.hdl b/02/FullAdder.hdl
index 8c987be..48b9dc2 100644
--- a/02/FullAdder.hdl
+++ b/02/FullAdder.hdl
@@ -11,5 +11,8 @@ CHIP FullAdder {
         carry;   // Left bit of a + b + c
 
     PARTS:
-    //// Replace this comment with your code.
-}
\ No newline at end of file
+    // Two half adders + OR gate
+    HalfAdder(a=a, b=b, sum=tmp1, carry=tmp2);
+    HalfAdder(a=tmp1, b=c, sum=sum, carry=tmp3);
+    Or(a=tmp2, b=tmp3, out=carry);
+}
diff --git a/02/HalfAdder.hdl b/02/HalfAdder.hdl
index 4f5900a..e3f334d 100644
--- a/02/HalfAdder.hdl
+++ b/02/HalfAdder.hdl
@@ -7,9 +7,11 @@
  */
 CHIP HalfAdder {
     IN a, b;    // 1-bit inputs
-    OUT sum,    // Right bit of a + b 
+    OUT sum,    // Right bit of a + b
         carry;  // Left bit of a + b
 
     PARTS:
-    //// Replace this comment with your code.
+    // sum = a XOR b, carry = a AND b
+    Xor(a=a, b=b, out=sum);
+    And(a=a, b=b, out=carry);
 }
diff --git a/02/Inc16.hdl b/02/Inc16.hdl
index 00a1310..9663aee 100644
--- a/02/Inc16.hdl
+++ b/02/Inc16.hdl
@@ -11,5 +11,6 @@ CHIP Inc16 {
     OUT out[16];
 
     PARTS:
-    //// Replace this comment with your code.
-}
\ No newline at end of file
+    // Add 1 using Add16
+    Add16(a=in, b[0]=true, b[1..15]=false, out=out);
+}