diff --git a/03/a/RAM64.hdl b/03/a/RAM64.hdl
index 5997a78..a4776e7 100644
--- a/03/a/RAM64.hdl
+++ b/03/a/RAM64.hdl
@@ -13,7 +13,7 @@ CHIP RAM64 {
     OUT out[16];
 
     PARTS:
-    // find which RAM8 to load by address (from high three bits)
+    // send load to correct RAM8 (high 3 bits)
     DMux8Way(in=load, sel=address[3..5], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
 
     // 8 RAM8 chips (low 3 bits select register within each)
@@ -26,6 +26,6 @@ CHIP RAM64 {
     RAM8(in=in, load=load6, address=address[0..2], out=out6);
     RAM8(in=in, load=load7, address=address[0..2], out=out7);
 
-    // select which RAM8 output to send
+    // select out from correct RAM8
     Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[3..5], out=out);
 }
diff --git a/03/a/RAM8.hdl b/03/a/RAM8.hdl
index 74a30de..8841621 100644
--- a/03/a/RAM8.hdl
+++ b/03/a/RAM8.hdl
@@ -13,7 +13,7 @@ CHIP RAM8 {
     OUT out[16];
 
     PARTS:
-    // find which register to load by address
+    // send load to correct register
     DMux8Way(in=load, sel=address, a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
 
     // 8 registers to store data
@@ -26,6 +26,6 @@ CHIP RAM8 {
     Register(in=in, load=load6, out=out6);
     Register(in=in, load=load7, out=out7);
 
-    // select which registers output to send
+    // select out from correct register
     Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address, out=out);
 }
diff --git a/03/b/RAM16K.hdl b/03/b/RAM16K.hdl
index 0364f82..3de5a7a 100644
--- a/03/b/RAM16K.hdl
+++ b/03/b/RAM16K.hdl
@@ -13,7 +13,7 @@ CHIP RAM16K {
     OUT out[16];
 
     PARTS:
-    // find which RAM4K to load by address (from high two bits)
+    // send load to correct RAM4K (high 2 bits)
     DMux4Way(in=load, sel=address[12..13], a=load0, b=load1, c=load2, d=load3);
 
     // 4 RAM4K chips (low 12 bits select register within each)
@@ -22,6 +22,6 @@ CHIP RAM16K {
     RAM4K(in=in, load=load2, address=address[0..11], out=out2);
     RAM4K(in=in, load=load3, address=address[0..11], out=out3);
 
-    // select which RAM4K output to send
+    // select out from correct RAM4K
     Mux4Way16(a=out0, b=out1, c=out2, d=out3, sel=address[12..13], out=out);
 }
diff --git a/03/b/RAM4K.hdl b/03/b/RAM4K.hdl
index f9a57c1..f35b2af 100644
--- a/03/b/RAM4K.hdl
+++ b/03/b/RAM4K.hdl
@@ -13,7 +13,7 @@ CHIP RAM4K {
     OUT out[16];
 
     PARTS:
-    // find which RAM512 to load by address (from high three bits)
+    // send load to correct RAM512 (high 3 bits)
     DMux8Way(in=load, sel=address[9..11], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
 
     // 8 RAM512 chips (low 9 bits select register within each)
@@ -26,6 +26,6 @@ CHIP RAM4K {
     RAM512(in=in, load=load6, address=address[0..8], out=out6);
     RAM512(in=in, load=load7, address=address[0..8], out=out7);
 
-    // select which RAM512 output to send
+    // select out from correct RAM512
     Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[9..11], out=out);
 }
diff --git a/03/b/RAM512.hdl b/03/b/RAM512.hdl
index 8f5b6f4..311fc6a 100644
--- a/03/b/RAM512.hdl
+++ b/03/b/RAM512.hdl
@@ -13,7 +13,7 @@ CHIP RAM512 {
     OUT out[16];
 
     PARTS:
-    // find which RAM64 to load by address (from high three bits)
+    // send load to correct RAM64 (high 3 bits)
     DMux8Way(in=load, sel=address[6..8], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
 
     // 8 RAM64 chips (low 6 bits select register within each)
@@ -26,6 +26,6 @@ CHIP RAM512 {
     RAM64(in=in, load=load6, address=address[0..5], out=out6);
     RAM64(in=in, load=load7, address=address[0..5], out=out7);
 
-    // select which RAM64 output to send
+    // select out from correct RAM64
     Mux8Way16(a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[6..8], out=out);
 }